1. Field of the Invention
The invention is related to computing systems and more particularly to multi-memory request scheduling in computing systems.
2. Description of the Related Art
In a typical computing system, a memory controller is an intermediary between a processor (e.g., central processing unit, digital signal processor, processor core, or core) and main memory (e.g., synchronous dynamic random access memory, i.e., SDRAM) that prioritizes and schedules memory requests (e.g., reads and writes from and to main memory, respectively). The memory controller schedules memory requests by prioritizing memory requests, translating the memory requests into a sequence of memory commands, and issuing to memory the sequence of memory commands associated with a highest priority memory request. A typical processing system (e.g., a chip multiprocessor system) includes multiple memory controllers and multiple memory channels for accessing main memory. Each memory controller controls a different portion of main memory. Each processor can access the portion of main memory controlled by any of the memory controllers in the system, thereby providing a large physical memory space to each processor. Accordingly, multiple processors in the multi-processor system may contend with each other for memory bandwidth. Thus, there is a need to facilitate memory request scheduling in processing systems.